Version 1.1 rev. a

Syllabus for basic VHDL-course

Operators:

                                      +, -, *, /, =, /=, <, <=, >, >=, **, &
                                       not, and, or, xor, nand, nor, xnor

Reserved words:

after, architecture, begin, case, component, constant, downto, else, elsif, end, entity,
for, if, in, inout, is, label, map, of, others, out, port, port map, process, range, signal,
then, to, type, until, (variable,) (wait,) when, while

  Types:

                                     integer, enumerated, physical (only TIME),
  
                                  bit, bit_vector, Boolean, std_logic, std_logic_vector

  Description:

Concurrent, sequential, behavioural, data flow.

 Attributes for signals:

                                    ‘event